1. Field of the Invention
This invention relates to an improved radiation hardened CMOS register, and more particularly to a resistive hardening which does not adversely affect the register write time.
2. Description of the Prior Art
As will be appreciated by those skilled in the art, semiconductor data storage circuits struck by high energy particles in a space environment can lose data due to the ionizing effects of the impact. In the prior art, designs that add resistive coupling between stages of a bi-stable CMOS circuit have been used to provide hardening (i.e. immunity) to these so called single event upset (SEU) phenomena. The interstage resistive coupling is effective in providing hardening against upsets from high energy particles, but this approach increases the time to write data into the element. The prior art has also used circuit designs for hardening that do not use resistive interstage coupling.
FIG. 1 shows a common prior art resistive coupling approach to radiation hardening a CMOS random access memory (RAM) cell; see for example U.S. Pat. No. 5,053,848. Lightly doped polysilicon resistors 10 and 12 are formed in the feedback paths between the two CMOS invertors 14 and 16, which comprise the RAM cell.
FIG. 2 shows an unhardened prior art register element, typical of that used in commercial designs. CMOS transistors P1, N1 and P4, N4, are used to access data storage invertors P2-N2 and P3-N3 and to provide a regeneration feedback loop. When signals CLK and CLK* are active, write access to the data storage transistors is provided through an input D and a CMOS transmission gate P1-N1. With CLK and CLK* active, the feedback transistors, P4 and N4 are turned off, allowing the input at D to force nodes A, B, and C to the proper logic levels. When CLK and CLK* are inactive, access through P1 and N1 ceases, and the regenerative feedback from node C to node A is completed by the CMOS transmission gate formed by P4 and N4.
FIG. 3 shows a typical resistive approach to hardening the register element shown in FIG. 2. In this prior art approach, resistors A and B are inserted respectively into the inputs of each inverter, P2-N2 and P3-N3. Like the RAM cell shown in FIG. 1, this approach adversely affects the write time to the register, as the times required to charge nodes A and B are a function of the series resistance and gate capacitance of the inverter stages. Thus, the time discrimination function provided by the RC time constant provides SEU immunity, but adversely affects the write time.
Other techniques for providing SEU immunity, which do not rely on resistive induced delay for hardening, are also known in the prior art. These techniques provide a high level of SEU immunity without adversely affecting the write setup time as does resistive hardening. However, these other techniques increase transistor count, circuit complexity, and require more silicon area.